1. general description the 74lvc1g57 provides config urable multiple functions. th e output state is determined by eight patterns of 3-bit input. the user can choose the logic functions and, or, nand, nor, xnor, inverter and buffer. all inputs can be connected to v cc or gnd. inputs can be driven from either 3.3 v or 5 v devi ces. this feature allows the use of this device in a mixed 3.3 v and 5 v environment. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventin g the damaging backflow current through the device when it is powered down. all inputs (a, b and c) are schmitt trigger inpu ts. they are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. features and benefits ? wide supply voltage range from 1.65 v to 5.5 v ? 5 v tolerant input/ output for interfacing with 5 v logic ? high noise immunity ? complies with jedec standard: ? jesd8-7 (1.65 v to 1.95 v) ? jesd8-5 (2.3 v to 2.7 v) ? jesd8b/jesd36 (2.7 v to 3.6 v). ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? ? 24 ma output drive (v cc =3.0v) ? cmos low power consumption ? latch-up performance exceeds 250 ma ? direct interface with ttl levels ? inputs accept voltages up to 5 v ? multiple package options ? specified from ? 40 ? cto+85 ? c and ? 40 ? cto+125 ? c. 74lvc1g57 low-power configurable multiple function gate rev. 8 7 december 2016 product data sheet downloaded from: http:///
? nexperia b.v. 2017. all rights reserved 74lvc1g57 all information provided in this document is subject to legal disclaimers. product data sheet rev. 8 7 december 2016 2 of 20 nexperia 74lvc1g57 low-power configurable multiple function gate 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74lvc1g57gw ? 40 ? cto+125 ? c sc-88 plastic surface-mounted package; 6 leads sot363 74lvc1g57gv ? 40 ? cto+125 ? c sc-74 plastic surface-mounted package; 6 leads sot457 74lvc1g57gm ? 40 ? cto+125 ? c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 ? 1.45 ? 0.5 mm sot886 74LVC1G57GF ? 40 ? cto+125 ? c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 ? 1 ? 0.5 mm sot891 74lvc1g57gn ? 40 ? c to +125 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 0.9 ? 1.0 ? 0.35 mm sot1115 74lvc1g57gs ? 40 ? c to +125 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 1.0 ? 1.0 ? 0.35 mm sot1202 table 2. marking type number marking code [1] 74lvc1g57gw yc 74lvc1g57gv v57 74lvc1g57gm yc 74LVC1G57GF yc 74lvc1g57gn yc 74lvc1g57gs yc fig 1. logic symbol < & % $ d d e downloaded from: http:///
? nexperia b.v. 2017. all rights reserved 74lvc1g57 all information provided in this document is subject to legal disclaimers. product data sheet rev. 8 7 december 2016 3 of 20 nexperia 74lvc1g57 low-power configurable multiple function gate 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level. fig 2. pin configuration sot363 and sot457 fig 3. pin configuration sot886 fig 4. pin configuration sot891, sot1115 and sot1202 / 9 & |